mirror of https://github.com/YosysHQ/yosys.git
21 lines
389 B
Verilog
21 lines
389 B
Verilog
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module decoder_always (in,out);
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input [2:0] in;
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output [7:0] out;
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reg [7:0] out;
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always @ (in)
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begin
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out = 0;
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case (in)
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3'b001 : out = 8'b0000_0001;
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3'b010 : out = 8'b0000_0010;
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3'b011 : out = 8'b0000_0100;
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3'b100 : out = 8'b0000_1000;
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3'b101 : out = 8'b0001_0000;
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3'b110 : out = 8'b0100_0000;
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3'b111 : out = 8'b1000_0000;
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endcase
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end
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endmodule
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