mirror of https://github.com/YosysHQ/yosys.git
14 lines
134 B
Verilog
14 lines
134 B
Verilog
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module reg_combo_example( a, b, y);
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input a, b;
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output y;
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reg y;
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wire a, b;
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always @ ( a or b)
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begin
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y = a & b;
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end
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endmodule
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