mirror of https://github.com/YosysHQ/yosys.git
9 lines
130 B
Verilog
9 lines
130 B
Verilog
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module encoder_4to2_gates (i0,i1,i2,i3,y);
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input i0,i1,i2,i3;
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output [1:0] y;
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or o1 (y[0],i1,i3);
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or o2 (y[1],i2,i3);
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endmodule
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