mirror of https://github.com/YosysHQ/yosys.git
44 lines
1.2 KiB
Verilog
44 lines
1.2 KiB
Verilog
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//-----------------------------------------------------
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// Design Name : decoder_using_case
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// File Name : decoder_using_case.v
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// Function : decoder using case
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module decoder_using_case (
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binary_in , // 4 bit binary input
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decoder_out , // 16-bit out
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enable // Enable for the decoder
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);
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input [3:0] binary_in ;
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input enable ;
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output [15:0] decoder_out ;
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reg [15:0] decoder_out ;
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always @ (enable or binary_in)
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begin
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decoder_out = 0;
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if (enable) begin
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case (binary_in)
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4'h0 : decoder_out = 16'h0001;
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4'h1 : decoder_out = 16'h0002;
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4'h2 : decoder_out = 16'h0004;
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4'h3 : decoder_out = 16'h0008;
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4'h4 : decoder_out = 16'h0010;
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4'h5 : decoder_out = 16'h0020;
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4'h6 : decoder_out = 16'h0040;
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4'h7 : decoder_out = 16'h0080;
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4'h8 : decoder_out = 16'h0100;
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4'h9 : decoder_out = 16'h0200;
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4'hA : decoder_out = 16'h0400;
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4'hB : decoder_out = 16'h0800;
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4'hC : decoder_out = 16'h1000;
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4'hD : decoder_out = 16'h2000;
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4'hE : decoder_out = 16'h4000;
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4'hF : decoder_out = 16'h8000;
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endcase
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end
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end
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endmodule
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