mirror of https://github.com/YosysHQ/yosys.git
30 lines
349 B
Verilog
30 lines
349 B
Verilog
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module d_ff_gates(d,clk,q,q_bar);
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input d,clk;
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output q, q_bar;
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wire n1,n2,n3,q_bar_n;
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wire cn,dn,n4,n5,n6;
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// First Latch
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not (n1,d);
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nand (n2,d,clk);
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nand (n3,n1,clk);
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nand (dn,q_bar_n,n2);
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nand (q_bar_n,dn,n3);
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// Second Latch
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not (cn,clk);
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not (n4,dn);
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nand (n5,dn,cn);
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nand (n6,n4,cn);
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nand (q,q_bar,n5);
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nand (q_bar,q,n6);
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endmodule
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