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15 lines
179 B
Plaintext
15 lines
179 B
Plaintext
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read_verilog <<EOT
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module half_clock (CLK, Q);
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input CLK;
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output reg Q;
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reg magic;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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abstract -state -enablen magic
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# show
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