2024-03-01 03:49:48 -06:00
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read_verilog ../common/tribuf.v
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hierarchy -top tristate
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proc
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tribuf
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flatten
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synth
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2024-07-24 06:29:51 -05:00
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equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore # equivalency check
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2024-03-01 03:49:48 -06:00
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd tristate # Constrain all select calls below inside the top module
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#Internal cell type used. Need support it.
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2024-05-07 02:06:10 -05:00
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select -assert-count 1 t:NX_IOB
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select -assert-count 2 t:NX_IOB_I
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select -assert-none t:NX_IOB t:NX_IOB_I %% t:* %D
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