mirror of https://github.com/YosysHQ/yosys.git
46 lines
870 B
Coq
46 lines
870 B
Coq
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`timescale 1 ns / 1 ps
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module testbench;
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reg rd_clk;
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reg [ 7:0] rd_addr;
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wire [15:0] rd_data;
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wire wr_clk = 0;
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wire wr_enable = 0;
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wire [ 7:0] wr_addr = 0;
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wire [15:0] wr_data = 0;
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myram uut (
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.rd_clk (rd_clk ),
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.rd_addr (rd_addr ),
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.rd_data (rd_data ),
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.wr_clk (wr_clk ),
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.wr_enable(wr_enable),
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.wr_addr (wr_addr ),
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.wr_data (wr_data )
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);
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initial begin
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rd_clk = 0;
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#1000;
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forever #10 rd_clk <= ~rd_clk;
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end
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integer i;
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initial begin
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rd_addr <= 0;
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@(posedge rd_clk);
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for (i = 0; i < 256; i=i+1) begin
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rd_addr <= rd_addr + 1;
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@(posedge rd_clk);
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// $display("%3d %3d", i, rd_data);
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if (i != rd_data) begin
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$display("[%1t] ERROR: addr=%3d, data=%3d", $time, i, rd_data);
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$stop;
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end
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end
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$display("[%1t] Passed bram2 test.", $time);
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$finish;
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end
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endmodule
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