mirror of https://github.com/YosysHQ/yosys.git
25 lines
432 B
Coq
25 lines
432 B
Coq
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module myram(
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input rd_clk,
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input [ 7:0] rd_addr,
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output reg [15:0] rd_data,
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input wr_clk,
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input wr_enable,
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input [ 7:0] wr_addr,
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input [15:0] wr_data
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);
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reg [15:0] memory [0:255];
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integer i;
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initial begin
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for (i = 0; i < 256; i = i+1)
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memory[i] = i;
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end
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always @(posedge rd_clk)
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rd_data <= memory[rd_addr];
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always @(posedge wr_clk)
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if (wr_enable)
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memory[wr_addr] <= wr_data;
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endmodule
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