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8 lines
187 B
Plaintext
8 lines
187 B
Plaintext
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proc
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memory
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equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40
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synth_ice40
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select -assert-count 8 t:SB_DFF
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select -assert-count 512 t:SB_DFFE
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write_verilog ./temp/memory_synth.v
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