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6 lines
178 B
Plaintext
6 lines
178 B
Plaintext
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synth_ice40
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equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40
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select -assert-count 89 t:SB_LUT4
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select -assert-count 66 t:SB_CARRY
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write_verilog ./temp/div_mod_synth.v
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