mirror of https://github.com/YosysHQ/yosys.git
18 lines
239 B
Plaintext
18 lines
239 B
Plaintext
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read_verilog <<EOT
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module uut(
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input a,
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output y, z
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);
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assign y = a == a;
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assign z = a != a;
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endmodule
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EOT
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copy uut after
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opt_expr after
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clean
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show -format dot -prefix opt_expr_full -notitle -color cornflowerblue uut
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