mirror of https://github.com/YosysHQ/yosys.git
64 lines
2.0 KiB
Coq
64 lines
2.0 KiB
Coq
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//====================================================
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// This is FSM demo program using single always
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// for both seq and combo logic
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// Design Name : fsm_using_single_always
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// File Name : fsm_using_single_always.v
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//=====================================================
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module fsm_using_single_always (
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clock , // clock
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reset , // Active high, syn reset
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req_0 , // Request 0
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req_1 , // Request 1
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gnt_0 , // Grant 0
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gnt_1
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);
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//=============Input Ports=============================
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input clock,reset,req_0,req_1;
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//=============Output Ports===========================
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output gnt_0,gnt_1;
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//=============Input ports Data Type===================
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wire clock,reset,req_0,req_1;
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//=============Output Ports Data Type==================
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reg gnt_0,gnt_1;
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//=============Internal Constants======================
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parameter SIZE = 3 ;
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parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
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//=============Internal Variables======================
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reg [SIZE-1:0] state ;// Seq part of the FSM
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reg [SIZE-1:0] next_state ;// combo part of FSM
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//==========Code startes Here==========================
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always @ (posedge clock)
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begin : FSM
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if (reset == 1'b1) begin
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state <= #1 IDLE;
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gnt_0 <= 0;
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gnt_1 <= 0;
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end else
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case(state)
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IDLE : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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gnt_0 <= 1;
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end else if (req_1 == 1'b1) begin
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gnt_1 <= 1;
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state <= #1 GNT1;
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end else begin
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state <= #1 IDLE;
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end
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GNT0 : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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end else begin
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gnt_0 <= 0;
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state <= #1 IDLE;
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end
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GNT1 : if (req_1 == 1'b1) begin
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state <= #1 GNT1;
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end else begin
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gnt_1 <= 0;
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state <= #1 IDLE;
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end
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default : state <= #1 IDLE;
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endcase
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end
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endmodule // End of Module arbiter
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