mirror of https://github.com/YosysHQ/yosys.git
43 lines
1.1 KiB
Verilog
43 lines
1.1 KiB
Verilog
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//-----------------------------------------------------
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// Design Name : encoder_using_case
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// File Name : encoder_using_case.v
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// Function : Encoder using Case
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module encoder_using_case(
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binary_out , // 4 bit binary Output
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encoder_in , // 16-bit Input
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enable // Enable for the encoder
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);
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output [3:0] binary_out ;
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input enable ;
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input [15:0] encoder_in ;
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reg [3:0] binary_out ;
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always @ (enable or encoder_in)
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begin
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binary_out = 0;
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if (enable) begin
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case (encoder_in)
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16'h0002 : binary_out = 1;
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16'h0004 : binary_out = 2;
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16'h0008 : binary_out = 3;
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16'h0010 : binary_out = 4;
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16'h0020 : binary_out = 5;
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16'h0040 : binary_out = 6;
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16'h0080 : binary_out = 7;
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16'h0100 : binary_out = 8;
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16'h0200 : binary_out = 9;
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16'h0400 : binary_out = 10;
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16'h0800 : binary_out = 11;
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16'h1000 : binary_out = 12;
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16'h2000 : binary_out = 13;
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16'h4000 : binary_out = 14;
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16'h8000 : binary_out = 15;
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endcase
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end
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end
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endmodule
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