mirror of https://github.com/YosysHQ/yosys.git
77 lines
1.8 KiB
Verilog
77 lines
1.8 KiB
Verilog
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(* abc9_lut=1, lib_whitebox *)
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module LUT1 (
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output O,
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input I0
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);
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parameter [1:0] INIT = 0;
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parameter EQN = "(I0)";
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// These timings are for PolarPro 3E; other families will need updating.
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specify
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(I0 => O) = 698; // FS -> FZ
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endspecify
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assign O = I0 ? INIT[1] : INIT[0];
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endmodule
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// TZ TSL TAB
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(* abc9_lut=2, lib_whitebox *)
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module LUT2 (
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output O,
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input I0, I1
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);
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parameter [3:0] INIT = 4'h0;
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parameter EQN = "(I0)";
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// These timings are for PolarPro 3E; other families will need updating.
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specify
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(I0 => O) = 1251; // TAB -> TZ
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(I1 => O) = 1406; // TSL -> TZ
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endspecify
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wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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(* abc9_lut=2, lib_whitebox *)
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module LUT3 (
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output O,
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input I0, I1, I2
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);
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parameter [7:0] INIT = 8'h0;
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parameter EQN = "(I0)";
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// These timings are for PolarPro 3E; other families will need updating.
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specify
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(I0 => O) = 1251; // TAB -> TZ
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(I1 => O) = 1406; // TSL -> TZ
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(I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ
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endspecify
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wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
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wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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(* abc9_lut=4, lib_whitebox *)
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module LUT4 (
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output O,
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input I0, I1, I2, I3
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);
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parameter [15:0] INIT = 16'h0;
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parameter EQN = "(I0)";
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// These timings are for PolarPro 3E; other families will need updating.
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specify
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(I0 => O) = 995; // TBS -> CZ
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(I1 => O) = 1437; // ('TAB', 'BAB') -> CZ
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(I2 => O) = 1593; // ('TSL', 'BSL') -> CZ
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(I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ
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endspecify
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wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
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wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
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wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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