mirror of https://github.com/YosysHQ/yosys.git
18 lines
233 B
Plaintext
18 lines
233 B
Plaintext
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ram block \RAM_WIDE_SDP {
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cost 2;
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abits 6;
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widths 1 2 5 10 20 per_port;
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byte 5;
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init any;
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port sr "R" {
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clock posedge;
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rden;
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rdsrst any ungated;
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}
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port sw "W" {
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clock posedge;
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wrtrans "R" old;
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wrbe_separate;
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}
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}
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