mirror of https://github.com/YosysHQ/yosys.git
15 lines
203 B
Verilog
15 lines
203 B
Verilog
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module decoder_2to4_gates (x,y,f0,f1,f2,f3);
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input x,y;
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output f0,f1,f2,f3;
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wire n1,n2;
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not i1 (n1,x);
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not i2 (n2,y);
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and a1 (f0,n1,n2);
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and a2 (f1,n1,y);
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and a3 (f2,x,n2);
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and a4 (f3,x,y);
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endmodule
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