mirror of https://github.com/YosysHQ/yosys.git
21 lines
346 B
Verilog
21 lines
346 B
Verilog
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module test (
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offset_i,
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data_o,
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data_ref_o
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);
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input wire [ 2:0] offset_i;
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output reg [15:0] data_o;
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output reg [15:0] data_ref_o;
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always @(*) begin
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// defaults
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data_o = '0;
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data_ref_o = '0;
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// partial assigns
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data_ref_o[offset_i+:4] = 4'b1111; // unsigned
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data_o[offset_i+:4] = 1'sb1; // sign extension to 4'b1111
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end
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endmodule
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