mirror of https://github.com/YosysHQ/yosys.git
8 lines
130 B
Systemverilog
8 lines
130 B
Systemverilog
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module top (
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input signed [1:0] a,
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input signed [2:0] b,
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output signed [4:0] c
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);
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assign c = 2'(a) * b;
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endmodule
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