yosys/tests/opt/opt_expr_constconn.ys

read_verilog opt_expr_constconn.v
select -assert-count 1 t:$add
select -assert-count 1 t:$add %ci w:C %i
equiv_opt -assert opt_expr
design -load postopt
select -assert-count 1 t:$add
select -assert-count 0 t:$add %ci w:C %i
opt_expr: Propagate constants to port connections. This adds one simple piece of functionality to opt_expr: when a cell port is connected to a fully-constant signal (as determined by sigmap), the port is reconnected directly to the constant value. This is just enough optimization to fix the "non-constant $meminit input" problem without requiring a full opt_clean or a separate pass. 2021-07-27 08:24:48 -05:00			`read_verilog opt_expr_constconn.v`
			`select -assert-count 1 t:$add`
			`select -assert-count 1 t:$add %ci w:C %i`
			`equiv_opt -assert opt_expr`
			`design -load postopt`
			`select -assert-count 1 t:$add`
			`select -assert-count 0 t:$add %ci w:C %i`