mirror of https://github.com/YosysHQ/yosys.git
37 lines
578 B
Verilog
37 lines
578 B
Verilog
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// expect-wr-ports 2
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// expect-rd-ports 1
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// expect-wr-wide-continuation 2'10
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module test(
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input clk,
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input [3:0] we,
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input [6:0] ra,
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input [5:0] wa,
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input [31:0] wd,
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output [15:0] rd
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);
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reg [7:0] mem[3:254];
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assign rd[7:0] = mem[{ra, 1'b0}];
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assign rd[15:0] = mem[{ra, 1'b1}];
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initial begin
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mem[5] = 8'h12;
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mem[6] = 8'h34;
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mem[7] = 8'h56;
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end
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always @(posedge clk) begin
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if (we[0])
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mem[{wa, 2'b00}] <= wd[7:0];
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if (we[1])
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mem[{wa, 2'b01}] <= wd[15:8];
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if (we[2])
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mem[{wa, 2'b10}] <= wd[23:16];
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if (we[3])
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mem[{wa, 2'b11}] <= wd[31:24];
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end
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endmodule
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