mirror of https://github.com/YosysHQ/yosys.git
46 lines
1.1 KiB
Verilog
46 lines
1.1 KiB
Verilog
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module RAM_WIDE_SDP #(
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parameter [79:0] INIT = 80'hx,
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parameter PORT_R_WIDTH = 1,
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parameter PORT_W_WIDTH = 1,
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parameter PORT_W_WR_BE_WIDTH = 1,
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parameter PORT_R_RD_SRST_VALUE = 16'hx
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) (
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input PORT_R_CLK,
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input PORT_R_RD_EN,
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input PORT_R_RD_SRST,
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input [5:0] PORT_R_ADDR,
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output reg [PORT_R_WIDTH-1:0] PORT_R_RD_DATA,
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input PORT_W_CLK,
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input PORT_W_WR_EN,
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input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE,
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input [5:0] PORT_W_ADDR,
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA
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);
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reg [79:0] mem;
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initial mem = INIT;
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always @(posedge PORT_R_CLK)
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if (PORT_R_RD_SRST)
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PORT_R_RD_DATA <= PORT_R_RD_SRST_VALUE;
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else if (PORT_R_RD_EN)
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PORT_R_RD_DATA <= mem[PORT_R_ADDR[5:2] * 5 + PORT_R_ADDR[1:0]+:PORT_R_WIDTH];
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generate
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if (PORT_W_WIDTH < 5) begin
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always @(posedge PORT_W_CLK)
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if (PORT_W_WR_EN && PORT_W_WR_BE[0])
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mem[PORT_W_ADDR[5:2] * 5 + PORT_W_ADDR[1:0]+:PORT_W_WIDTH] <= PORT_W_WR_DATA;
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end else begin
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integer i;
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always @(posedge PORT_W_CLK)
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if (PORT_W_WR_EN)
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for (i = 0; i < PORT_W_WR_BE_WIDTH; i = i + 1)
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if (PORT_W_WR_BE[i])
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mem[(PORT_W_ADDR[5:2] + i) * 5+:5] <= PORT_W_WR_DATA[i * 5+:5];
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end
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endgenerate
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endmodule
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