yosys/tests/arch/efinix/add_sub.ys

read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:EFX_ADD
select -assert-count 4  t:EFX_LUT4
select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
Share common tests 2019-10-18 05:19:59 -05:00			`read_verilog ../common/add_sub.v`
Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. 2019-09-23 07:51:41 -05:00			`hierarchy -top top`
hierarchy - proc reorder 2019-10-18 02:13:06 -05:00			`proc`
Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. 2019-09-23 07:51:41 -05:00			`equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check`
			`design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)`
			`cd top # Constrain all select calls below inside the top module`
			`select -assert-count 10 t:EFX_ADD`
			`select -assert-count 4 t:EFX_LUT4`
			`select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D`