mirror of https://github.com/YosysHQ/yosys.git
12 lines
191 B
Plaintext
12 lines
191 B
Plaintext
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read_verilog counter.v
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read_verilog -lib cmos_cells.v
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proc;; memory;; techmap;;
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dfflibmap -liberty cmos_cells.lib
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abc -liberty cmos_cells.lib;;
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write_verilog synth.v
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write_spice synth.sp
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