2019-10-18 05:19:59 -05:00
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read_verilog ../common/logic.v
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2019-09-03 03:53:37 -05:00
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hierarchy -top top
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2019-10-18 02:04:02 -05:00
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proc
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2019-09-04 04:15:52 -05:00
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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2019-09-03 03:53:37 -05:00
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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2019-09-04 04:15:52 -05:00
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select -assert-count 9 t:LUT4
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select -assert-none t:LUT4 %% t:* %D
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