mirror of https://github.com/YosysHQ/yosys.git
324 lines
10 KiB
Python
324 lines
10 KiB
Python
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#!/usr/bin/env python3
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class FNode:
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def __init__(self, fun, *args):
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self.fun = fun
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self.args = args
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if len(self.args) == 0:
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assert fun not in ("BUF", "NOT", "AND", "OR", "XOR", "MUX")
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if len(self.args) == 1:
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assert fun in ("BUF", "NOT")
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if len(self.args) == 2:
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assert fun in ("AND", "OR", "XOR")
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if len(self.args) == 3:
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assert fun in ("MUX")
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def __str__(self):
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if len(self.args) == 0:
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return self.fun
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if self.fun == "NOT" and len(self.args[0].args) == 0:
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return "!" + self.args[0].fun
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return self.fun + "(" + ",".join([str(a) for a in self.args]) + ")"
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def as_genlib_term(self):
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if len(self.args) == 0:
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return self.fun
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if self.fun == "NOT":
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assert len(self.args[0].args) == 0
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return "!" + self.args[0].fun
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if self.fun == "AND":
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return "(" + self.args[0].as_genlib_term() + "*" + self.args[1].as_genlib_term() + ")"
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if self.fun == "OR":
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return "(" + self.args[0].as_genlib_term() + "+" + self.args[1].as_genlib_term() + ")"
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assert False
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def mapMux(self):
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if self.fun == "MUX":
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A, B, C = self.args
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return OR(AND(A, NOT(C)), AND(B, C)).mapMux()
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return FNode(self.fun, *[a.mapMux() for a in self.args])
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def mapXor(self):
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if self.fun == "XOR":
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A, B = self.args
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return OR(AND(A, NOT(B)), AND(NOT(A), B)).mapXor()
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return FNode(self.fun, *[a.mapXor() for a in self.args])
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def mapNot(self):
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if self.fun == "BUF":
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return self.arg1.mapNot()
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if self.fun == "NOT":
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if self.args[0].fun == "AND":
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return OR(NOT(self.args[0].args[0]),NOT(self.args[0].args[1])).mapNot()
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if self.args[0].fun == "OR":
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return AND(NOT(self.args[0].args[0]),NOT(self.args[0].args[1])).mapNot()
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if self.args[0].fun == "NOT":
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return self.args[0].args[0].mapNot()
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return FNode(self.fun, *[a.mapNot() for a in self.args])
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def map(self):
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n = self
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n = n.mapMux()
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n = n.mapXor()
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n = n.mapNot()
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return n
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def isInv(self):
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if len(self.args) == 0:
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return False
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if self.fun == "XOR":
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return False
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if self.fun == "NOT":
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return self.args[0].isNonInv()
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for a in self.args:
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if not a.isInv():
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return False
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return True
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def isNonInv(self):
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if len(self.args) == 0:
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return True
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if self.fun == "XOR":
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return False
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if self.fun == "NOT":
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return self.args[0].isInv()
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for a in self.args:
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if not a.isNonInv():
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return False
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return True
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A = FNode("A")
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B = FNode("B")
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C = FNode("C")
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D = FNode("D")
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E = FNode("E")
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def BUF(arg): return FNode("BUF", arg)
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def NOT(arg): return FNode("NOT", arg)
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def AND(arg1, arg2): return FNode("AND", arg1, arg2)
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def OR(arg1, arg2): return FNode( "OR", arg1, arg2)
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def XOR(arg1, arg2): return FNode("XOR", arg1, arg2)
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def MUX(arg1, arg2, arg3): return FNode("MUX", arg1, arg2, arg3)
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# Genlib Format:
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#
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# GATE <cell-name> <cell-area> <cell-logic-function>
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#
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# PIN <pin-name> <phase> <input-load> <max-load>
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# <rise-block-delay> <rise-fanout-delay>
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# <fall-block-delay> <fall-fanout-delay>
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#
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# phase:
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# INV, NONINV, or UNKNOWN
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#
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# cell-logic-function:
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# <output> = <term with *(AND), +(OR), !(NOT)>
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cells = [
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["$__CC_BUF", 5, A],
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["$__CC_NOT", 0, NOT(A)],
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["$__CC_MUX", 5, MUX(A, B, C)],
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]
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base_cells = [
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["$__CC2_A", AND(A, B)],
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["$__CC2_O", OR(A, B)],
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["$__CC2_X", XOR(A, B)],
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["$__CC3_AA", AND(AND(A, B), C)],
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["$__CC3_OO", OR( OR(A, B), C)],
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["$__CC3_XX", XOR(XOR(A, B), C)],
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["$__CC3_AO", OR(AND(A, B), C)],
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["$__CC3_OA", AND( OR(A, B), C)],
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["$__CC3_AX", XOR(AND(A, B), C)],
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["$__CC3_XA", AND(XOR(A, B), C)],
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# ["$__CC3_AAA", AND(AND(A,B),AND(A,C))],
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# ["$__CC3_AXA", XOR(AND(A,B),AND(A,C))],
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# ["$__CC3_XAX", AND(XOR(A,B),XOR(A,C))],
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# ["$__CC3_AAX", AND(AND(A,B),XOR(A,C))],
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# ["$__CC3_AXX", XOR(AND(A,B),XOR(A,C))],
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# ["$__CC3_XXX", XOR(XOR(A,B),XOR(A,C))],
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# ["$__CC3_AAO", AND(AND(A,B), OR(A,C))],
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# ["$__CC3_AOA", OR(AND(A,B),AND(A,C))],
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# ["$__CC3_AOX", OR(AND(A,B),XOR(A,C))],
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# ["$__CC3_AAA_N", AND(AND(A,B),AND(NOT(A),C))],
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# ["$__CC3_AXA_N", XOR(AND(A,B),AND(NOT(A),C))],
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# ["$__CC3_XAX_N", AND(XOR(A,B),XOR(NOT(A),C))],
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# ["$__CC3_AAX_N", AND(AND(A,B),XOR(NOT(A),C))],
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# ["$__CC3_AXX_N", XOR(AND(A,B),XOR(NOT(A),C))],
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# ["$__CC3_XXX_N", XOR(XOR(A,B),XOR(NOT(A),C))],
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# ["$__CC3_AAO_N", AND(AND(A,B), OR(NOT(A),C))],
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# ["$__CC3_AOA_N", OR(AND(A,B),AND(NOT(A),C))],
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# ["$__CC3_AOX_N", OR(AND(A,B),XOR(NOT(A),C))],
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["$__CC4_AAA", AND(AND(A,B),AND(C,D))],
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["$__CC4_AXA", XOR(AND(A,B),AND(C,D))],
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["$__CC4_XAX", AND(XOR(A,B),XOR(C,D))],
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["$__CC4_AAX", AND(AND(A,B),XOR(C,D))],
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["$__CC4_AXX", XOR(AND(A,B),XOR(C,D))],
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["$__CC4_XXX", XOR(XOR(A,B),XOR(C,D))],
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["$__CC4_AAO", AND(AND(A,B), OR(C,D))],
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["$__CC4_AOA", OR(AND(A,B),AND(C,D))],
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["$__CC4_AOX", OR(AND(A,B),XOR(C,D))],
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]
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for name, expr in base_cells:
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cells.append([name, 10, expr])
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name = (name
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.replace("$__CC4_", "$__CC5_")
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.replace("$__CC3_", "$__CC4_")
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.replace("$__CC2_", "$__CC3_"))
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# Cells such as $__CC4_AA_A are redundant, as $__CC4_AAA is equivalent
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if name not in ("$__CC4_AA", "$__CC3_A"):
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cells.append([name + "_A", 12, AND(E, expr)])
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if name not in ("$__CC4_OO", "$__CC3_O"):
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cells.append([name + "_O", 12, OR(E, expr)])
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if name not in ("$__CC4_XX", "$__CC3_X"):
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cells.append([name + "_X", 12, XOR(E, expr)])
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with open("techlibs/gatemate/lut_tree_cells.genlib", "w") as glf:
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def mkGate(name, cost, expr, max_load=9999, block_delay = 10, fanout_delay = 5):
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name = name.replace(" ", "")
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expr = expr.map()
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phase = "UNKNOWN"
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if expr.isInv(): phase = "INV"
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if expr.isNonInv(): phase = "NONINV"
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print("", file=glf)
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print("GATE %s %d Y=%s;" % (name, cost, expr.as_genlib_term()), file=glf)
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print("PIN * %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf)
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print("GATE $__ZERO 0 Y=CONST0;", file=glf)
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print("GATE $__ONE 0 Y=CONST1;", file=glf)
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for name, cost, expr in cells:
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mkGate(name, cost, expr)
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class LUTTreeNode:
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def __init__(self, name, width, inputs=None):
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self.name = name
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self.width = width
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self.inputs = inputs
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def is_input(self):
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return self.width == 0
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def map(self, expr, params, ports):
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if self.is_input():
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# Input to LUT tree
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if expr is None:
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ports[self.name] = "" # disconnected input
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else:
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assert(len(expr.args) == 0)
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ports[self.name] = expr.fun
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return
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if expr is None:
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# Unused part of tree
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params[self.name] = "4'b0000"
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for i in self.inputs:
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i.map(None, params, ports)
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return
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elif len(expr.args) == 0:
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# Input to the expression; but not LUT tree
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# Insert a route through
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params[self.name] = "4'b1010"
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self.inputs[0].map(expr, params, ports)
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for i in self.inputs[1:]:
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i.map(None, params, ports)
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return
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# Map uphill LUTs; uninverting arguments and keeping track of that if needed
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arg_inv = []
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for (i, arg) in zip(self.inputs, expr.args):
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if arg.fun == "NOT":
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i.map(arg.args[0], params, ports)
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arg_inv.append(True)
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else:
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i.map(arg, params, ports)
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arg_inv.append(False)
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# Determine base init value
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assert self.width == 2
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if expr.fun == "AND":
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init = 0b1000
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elif expr.fun == "OR":
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init = 0b1110
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elif expr.fun == "XOR":
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init = 0b0110
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else:
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assert False, expr.fun
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# Swap bits if init inverted
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swapped_init = 0b0000
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for b in range(4):
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if ((init >> b) & 0x1) == 0: continue
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for i in range(2):
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if arg_inv[i]:
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b ^= (1 << i)
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swapped_init |= (1 << b)
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# Set init param
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params[self.name] = "4'b{:04b}".format(swapped_init)
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def LUT2(name, i0, i1): return LUTTreeNode(name, 2, [i0, i1])
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def I(name): return LUTTreeNode(name, 0)
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lut_prims = {
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"CC_LUT2": LUT2("INIT", I("I0"), I("I1")),
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"CC_L2T4": LUT2(
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"INIT_L10",
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LUT2("INIT_L00", I("I0"), I("I1")),
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LUT2("INIT_L01", I("I2"), I("I3")),
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),
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"CC_L2T5": LUT2(
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"INIT_L20", I("I4"), LUT2("INIT_L11",
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LUT2("INIT_L02", I("I0"), I("I1")),
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LUT2("INIT_L03", I("I2"), I("I3")),
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)
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)
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}
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with open("techlibs/gatemate/lut_tree_map.v", "w") as vf:
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# Non-automatic rules
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print("""
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module \\$__ZERO (output Y); assign Y = 1'b0; endmodule
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module \\$__ONE (output Y); assign Y = 1'b1; endmodule
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module \\$__CC_BUF (input A, output Y); assign Y = A; endmodule
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module \\$__CC_MUX (input A, B, C, output Y);
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CC_MX2 _TECHMAP_REPLACE_ (
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.D0(A), .D1(B), .S0(C),
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.Y(Y)
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);
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endmodule
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""", file=vf)
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for name, cost, expr in cells:
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expr = expr.mapMux().mapNot() # Don't map XOR
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if name in ("$__CC_BUF", "$__CC_NOT", "$__CC_MUX"):
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# Special cases
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continue
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if name.startswith("$__CC2_"):
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prim = "CC_LUT2"
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elif name.startswith("$__CC5_") or (name.startswith("$__CC4_") and cost == 12):
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prim = "CC_L2T5"
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else:
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prim = "CC_L2T4"
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ports = {}
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params = {}
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lut_prims[prim].map(expr, params, ports)
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print("", file=vf)
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print("module \\%s (input %s, output Y);" % (name,
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", ".join(sorted(set(x for x in ports.values() if x)))), file=vf)
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print(" %s #(" % prim, file=vf)
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for k, v in sorted(params.items(), key=lambda x: x[0]):
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print(" .%s(%s)," % (k, v), file=vf)
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print(" ) _TECHMAP_REPLACE_ (", file=vf)
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print(" %s," % ", ".join(".%s(%s)" % (k, v) for k, v in sorted(ports.items(), key=lambda x:x[0])),
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file=vf)
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print(" .O(Y)", file=vf)
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print(" );", file=vf)
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print("endmodule", file=vf)
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