mirror of https://github.com/YosysHQ/yosys.git
16 lines
276 B
Verilog
16 lines
276 B
Verilog
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module uut (clk, rst, out, counter);
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input clk, rst;
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output reg [7:0] out;
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output reg [4:0] counter;
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reg [7:0] memory [0:19];
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always @(posedge clk) begin
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counter <= rst || counter == 19 ? 0 : counter+1;
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memory[counter] <= counter;
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out <= memory[counter];
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end
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endmodule
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