mirror of https://github.com/YosysHQ/yosys.git
231 lines
7.8 KiB
Plaintext
231 lines
7.8 KiB
Plaintext
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read_verilog -icells <<EOT
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module sr0(input R, S, (* init = 3'h0 *) output [2:0] Q);
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$_SR_PP_ ff0 (.R(R), .S(S), .Q(Q[0]));
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$_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1]));
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$_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2]));
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endmodule
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module sr1(input R, S, (* init = 3'h7 *) output [2:0] Q);
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$_SR_PP_ ff0 (.R(R), .S(S), .Q(Q[0]));
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$_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1]));
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$_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2]));
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endmodule
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module top(input C, E, R, D, output [5:0] Q);
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sr0 sr0_(.S(S), .R(R), .Q(Q[2:0]));
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sr1 sr1_(.S(S), .R(R), .Q(Q[5:3]));
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endmodule
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EOT
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design -save orig
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flatten
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
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# Convert everything to SRs.
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design -load orig
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dfflegalize -cell $_SR_PP_ 0
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select -assert-count 2 sr0/t:$_NOT_
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select -assert-count 5 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_SR_PP_
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select -assert-count 3 sr1/t:$_SR_PP_
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select -assert-count 0 sr0/t:$_ANDNOT_
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select -assert-count 1 sr1/t:$_ANDNOT_
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select -assert-count 0 sr0/t:$_AND_
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select -assert-count 1 sr1/t:$_AND_
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select -assert-count 0 sr0/t:$_OR_
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select -assert-count 1 sr1/t:$_OR_
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select -assert-none t:$_SR_PP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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design -load orig
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dfflegalize -cell $_SR_PP_ 1
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select -assert-count 5 sr0/t:$_NOT_
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select -assert-count 2 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_SR_PP_
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select -assert-count 3 sr1/t:$_SR_PP_
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select -assert-count 1 sr0/t:$_ANDNOT_
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select -assert-count 0 sr1/t:$_ANDNOT_
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select -assert-count 1 sr0/t:$_AND_
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select -assert-count 0 sr1/t:$_AND_
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select -assert-count 1 sr0/t:$_OR_
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select -assert-count 0 sr1/t:$_OR_
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select -assert-none t:$_SR_PP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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# Convert everything to ADLATCHs.
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design -load orig
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dfflegalize -cell $_DLATCH_PP0_ 0
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select -assert-count 2 sr0/t:$_NOT_
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select -assert-count 5 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_DLATCH_PP0_
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select -assert-count 3 sr1/t:$_DLATCH_PP0_
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select -assert-count 0 sr0/t:$_ANDNOT_
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select -assert-count 1 sr1/t:$_ANDNOT_
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select -assert-count 0 sr0/t:$_AND_
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select -assert-count 1 sr1/t:$_AND_
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select -assert-count 0 sr0/t:$_OR_
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select -assert-count 1 sr1/t:$_OR_
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select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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design -load orig
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dfflegalize -cell $_DLATCH_PP0_ 1
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select -assert-count 5 sr0/t:$_NOT_
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select -assert-count 2 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_DLATCH_PP0_
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select -assert-count 3 sr1/t:$_DLATCH_PP0_
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select -assert-count 1 sr0/t:$_ANDNOT_
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select -assert-count 0 sr1/t:$_ANDNOT_
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select -assert-count 1 sr0/t:$_AND_
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select -assert-count 0 sr1/t:$_AND_
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select -assert-count 1 sr0/t:$_OR_
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select -assert-count 0 sr1/t:$_OR_
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select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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design -load orig
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dfflegalize -cell $_DLATCH_PP1_ 0
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select -assert-count 11 sr0/t:$_NOT_
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select -assert-count 8 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_DLATCH_PP1_
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select -assert-count 3 sr1/t:$_DLATCH_PP1_
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select -assert-count 1 sr0/t:$_ANDNOT_
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select -assert-count 0 sr1/t:$_ANDNOT_
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select -assert-count 1 sr0/t:$_AND_
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select -assert-count 0 sr1/t:$_AND_
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select -assert-count 1 sr0/t:$_OR_
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select -assert-count 0 sr1/t:$_OR_
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select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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design -load orig
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dfflegalize -cell $_DLATCH_PP1_ 1
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select -assert-count 8 sr0/t:$_NOT_
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select -assert-count 11 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_DLATCH_PP1_
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select -assert-count 3 sr1/t:$_DLATCH_PP1_
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select -assert-count 0 sr0/t:$_ANDNOT_
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select -assert-count 1 sr1/t:$_ANDNOT_
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select -assert-count 0 sr0/t:$_AND_
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select -assert-count 1 sr1/t:$_AND_
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select -assert-count 0 sr0/t:$_OR_
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select -assert-count 1 sr1/t:$_OR_
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select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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# Convert everything to DLATCHSRs.
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design -load orig
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dfflegalize -cell $_DLATCHSR_PPP_ 0
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select -assert-count 2 sr0/t:$_NOT_
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select -assert-count 5 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_DLATCHSR_PPP_
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select -assert-count 3 sr1/t:$_DLATCHSR_PPP_
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select -assert-count 0 sr0/t:$_ANDNOT_
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select -assert-count 1 sr1/t:$_ANDNOT_
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select -assert-count 0 sr0/t:$_AND_
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select -assert-count 1 sr1/t:$_AND_
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select -assert-count 0 sr0/t:$_OR_
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select -assert-count 1 sr1/t:$_OR_
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select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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design -load orig
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dfflegalize -cell $_DLATCHSR_PPP_ 1
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select -assert-count 5 sr0/t:$_NOT_
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select -assert-count 2 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_DLATCHSR_PPP_
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select -assert-count 3 sr1/t:$_DLATCHSR_PPP_
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select -assert-count 1 sr0/t:$_ANDNOT_
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select -assert-count 0 sr1/t:$_ANDNOT_
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select -assert-count 1 sr0/t:$_AND_
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select -assert-count 0 sr1/t:$_AND_
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select -assert-count 1 sr0/t:$_OR_
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select -assert-count 0 sr1/t:$_OR_
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select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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# Convert everything to DFFSRs.
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design -load orig
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dfflegalize -cell $_DFFSR_PPP_ 0
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select -assert-count 2 sr0/t:$_NOT_
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select -assert-count 5 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_DFFSR_PPP_
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select -assert-count 3 sr1/t:$_DFFSR_PPP_
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select -assert-count 0 sr0/t:$_ANDNOT_
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select -assert-count 1 sr1/t:$_ANDNOT_
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select -assert-count 0 sr0/t:$_AND_
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select -assert-count 1 sr1/t:$_AND_
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select -assert-count 0 sr0/t:$_OR_
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select -assert-count 1 sr1/t:$_OR_
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select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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design -load orig
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dfflegalize -cell $_DFFSR_PPP_ 1
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select -assert-count 5 sr0/t:$_NOT_
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select -assert-count 2 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_DFFSR_PPP_
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select -assert-count 3 sr1/t:$_DFFSR_PPP_
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select -assert-count 1 sr0/t:$_ANDNOT_
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select -assert-count 0 sr1/t:$_ANDNOT_
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select -assert-count 1 sr0/t:$_AND_
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select -assert-count 0 sr1/t:$_AND_
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select -assert-count 1 sr0/t:$_OR_
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select -assert-count 0 sr1/t:$_OR_
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select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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# Convert everything to DFFSREs.
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design -load orig
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dfflegalize -cell $_DFFSRE_PPPP_ 0
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select -assert-count 2 sr0/t:$_NOT_
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select -assert-count 5 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_DFFSRE_PPPP_
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select -assert-count 3 sr1/t:$_DFFSRE_PPPP_
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select -assert-count 0 sr0/t:$_ANDNOT_
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select -assert-count 1 sr1/t:$_ANDNOT_
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select -assert-count 0 sr0/t:$_AND_
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select -assert-count 1 sr1/t:$_AND_
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select -assert-count 0 sr0/t:$_OR_
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select -assert-count 1 sr1/t:$_OR_
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select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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design -load orig
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dfflegalize -cell $_DFFSRE_PPPP_ 1
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select -assert-count 5 sr0/t:$_NOT_
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select -assert-count 2 sr1/t:$_NOT_
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select -assert-count 3 sr0/t:$_DFFSRE_PPPP_
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select -assert-count 3 sr1/t:$_DFFSRE_PPPP_
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select -assert-count 1 sr0/t:$_ANDNOT_
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select -assert-count 0 sr1/t:$_ANDNOT_
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select -assert-count 1 sr0/t:$_AND_
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select -assert-count 0 sr1/t:$_AND_
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select -assert-count 1 sr0/t:$_OR_
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select -assert-count 0 sr1/t:$_OR_
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select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
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