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43 lines
1.1 KiB
Plaintext
43 lines
1.1 KiB
Plaintext
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read_verilog -icells <<EOT
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module dlatch(input E, D, output [1:0] Q);
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$_DLATCH_P_ ff0 (.E(E), .D(D), .Q(Q[0]));
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$_DLATCH_N_ ff1 (.E(E), .D(D), .Q(Q[1]));
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endmodule
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EOT
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design -save orig
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
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# Convert everything to DFFs.
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design -load orig
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dfflegalize -cell $_DLATCH_P_ x
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select -assert-count 1 t:$_NOT_
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select -assert-count 2 t:$_DLATCH_P_
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select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i
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# Convert everything to ADLATCHs.
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design -load orig
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dfflegalize -cell $_DLATCH_PP0_ x
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select -assert-count 1 t:$_NOT_
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select -assert-count 2 t:$_DLATCH_PP0_
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select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
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# Convert everything to DLATCHSRs.
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design -load orig
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dfflegalize -cell $_DLATCHSR_PPP_ x
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select -assert-count 1 t:$_NOT_
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select -assert-count 2 t:$_DLATCHSR_PPP_
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select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
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