mirror of https://github.com/YosysHQ/yosys.git
14 lines
173 B
Coq
14 lines
173 B
Coq
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module FlipFlop(clock, cs, ns);
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input clock;
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input [3:0] cs;
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output reg [3:0] ns;
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reg [3:0] temp;
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always @(posedge clock)
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begin
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temp = cs;
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ns = temp;
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end
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endmodule
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