2019-04-12 23:40:02 -05:00
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module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 4;
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parameter CFG_DBITS = 4;
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parameter [63:0] INIT = 64'bx;
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input CLK1;
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input [CFG_ABITS-1:0] A1ADDR;
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output [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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input [CFG_DBITS-1:0] B1DATA;
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input B1EN;
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`include "brams_init3.vh"
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2022-02-08 23:13:34 -06:00
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RAM16SDP4
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2019-04-12 23:40:02 -05:00
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#(.INIT_0(INIT_0),
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.INIT_1(INIT_1),
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.INIT_2(INIT_2),
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.INIT_3(INIT_3))
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_TECHMAP_REPLACE_
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2022-02-08 23:13:34 -06:00
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(.WAD(B1ADDR),
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.RAD(A1ADDR),
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2019-04-12 23:40:02 -05:00
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.DI(B1DATA),
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.DO(A1DATA),
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.CLK(CLK1),
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.WRE(B1EN));
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endmodule
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