yosys/tests/verilog/unbased_unsized_tern.ys

read_verilog -sv unbased_unsized_tern.sv
hierarchy
proc
equiv_make gold gate equiv
equiv_simple
equiv_status -assert
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change 2021-10-19 19:46:26 -05:00			`read_verilog -sv unbased_unsized_tern.sv`
			`hierarchy`
			`proc`
			`equiv_make gold gate equiv`
			`equiv_simple`
			`equiv_status -assert`