mirror of https://github.com/YosysHQ/yosys.git
15 lines
382 B
Verilog
15 lines
382 B
Verilog
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// http://www.reddit.com/r/yosys/comments/1vljks/new_support_for_systemveriloglike_asserts/
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module test(input clk, input rst, output y);
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reg [2:0] state;
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always @(posedge clk) begin
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if (rst || state == 3) begin
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state <= 0;
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end else begin
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assert(state < 3);
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state <= state + 1;
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end
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end
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assign y = state[2];
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assert property (y !== 1'b1);
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endmodule
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