mirror of https://github.com/YosysHQ/yosys.git
16 lines
622 B
Plaintext
16 lines
622 B
Plaintext
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read_verilog mul.v
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hierarchy -top top
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 12 t:LUT2
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select -assert-count 1 t:LUT3
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select -assert-count 6 t:LUT4
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select -assert-count 1 t:LUT5
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select -assert-count 33 t:LUT6
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select -assert-count 11 t:MUXCY
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select -assert-count 1 t:MUXF7
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select -assert-count 12 t:XORCY
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select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
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