mirror of https://github.com/YosysHQ/yosys.git
24 lines
411 B
Verilog
24 lines
411 B
Verilog
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module top(out);
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function integer operation;
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input integer num;
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begin
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operation = 0;
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begin : op_i
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integer i;
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for (i = 0; i < 2; i = i + 1)
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begin : op_j
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integer j;
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for (j = i; j < i * 2; j = j + 1)
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num = num + 1;
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end
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num = num * 2;
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end
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operation = num;
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end
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endfunction
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localparam res = operation(4);
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output wire [31:0] out;
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assign out = res;
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endmodule
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