mirror of https://github.com/YosysHQ/yosys.git
16 lines
318 B
Verilog
16 lines
318 B
Verilog
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module MYMUL(A, B, Y);
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parameter WIDTH = 1;
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input [WIDTH-1:0] A, B;
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output reg [WIDTH-1:0] Y;
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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integer i;
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always @* begin
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Y = 0;
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for (i = 0; i < WIDTH; i=i+1)
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if (A[i])
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Y = Y + (B << i);
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end
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endmodule
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