yosys/tests/verilog/prefix.ys

read_verilog -sv prefix.sv
hierarchy
proc
select -module top
sat -verify -seq 1 -prove-asserts -show-all
verilog: fix multiple AST_PREFIX scope resolution issues - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes 2021-08-02 19:42:34 -05:00			`read_verilog -sv prefix.sv`
			`hierarchy`
			`proc`
			`select -module top`
			`sat -verify -seq 1 -prove-asserts -show-all`