mirror of https://github.com/YosysHQ/yosys.git
12 lines
177 B
Plaintext
12 lines
177 B
Plaintext
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read_verilog <<EOT
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module top(input [31:0] a, input signed [2:0] x, output [2:0] o);
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wire [5:0] t = x * 3;
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assign o = a >> t;
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endmodule
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EOT
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wreduce
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equiv_opt -assert peepopt
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