mirror of https://github.com/YosysHQ/yosys.git
16 lines
336 B
Verilog
16 lines
336 B
Verilog
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// Exact reproduction of Figure 5(a) (bottom) from 10.1109/92.285741.
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module top(...);
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input a,b,c,d,e,f,g,h,i,j;
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wire x = !(a&b);
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wire y = !(c|d);
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wire z = !(e|f);
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wire n0 = !(g&h);
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wire n1 = !(i|j);
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wire w = !(x&y);
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wire n2 = !(z&n0);
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wire n3 = !(n0|n1);
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wire n4 = !(n2|n3);
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wire v = !(w|n5);
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output u = !(w&v);
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endmodule
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