mirror of https://github.com/YosysHQ/yosys.git
5 lines
133 B
Verilog
5 lines
133 B
Verilog
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module test(input [3:0] A, output [3:0] Y1, Y2);
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assign Y1 = |{A[3], 1'b0, A[1]};
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assign Y2 = |{A[2], 1'b1, A[0]};
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endmodule
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