mirror of https://github.com/YosysHQ/yosys.git
64 lines
903 B
Verilog
64 lines
903 B
Verilog
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module scopes_test_01(input [3:0] k, output reg [15:0] x, y);
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function [15:0] func_01;
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input [15:0] x, y;
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begin
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func_01 = x + y;
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begin:blk
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reg [15:0] x;
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x = y;
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func_01 = func_01 ^ x;
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end
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func_01 = func_01 ^ x;
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end
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endfunction
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function [15:0] func_02;
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input [15:0] x, y;
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begin
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func_02 = x - y;
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begin:blk
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reg [15:0] func_02;
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func_02 = 0;
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end
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end
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endfunction
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task task_01;
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input [3:0] a;
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reg [15:0] y;
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begin
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y = a * 23;
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x = x + y;
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end
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endtask
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task task_02;
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input [3:0] a;
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begin:foo
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reg [15:0] x, z;
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x = y;
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begin:bar
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reg [15:0] x;
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x = 77 + a;
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z = -x;
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end
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y = x ^ z;
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end
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endtask
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always @* begin
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x = func_01(11, 22);
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y = func_02(33, 44);
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task_01(k);
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task_02(k);
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begin:foo
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reg [15:0] y;
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y = x;
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y = y + k;
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x = y;
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end
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x = func_01(y, x);
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y = func_02(y, x);
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end
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endmodule
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