mirror of https://github.com/YosysHQ/yosys.git
14 lines
193 B
Verilog
14 lines
193 B
Verilog
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module uut_always02(clock, reset, count);
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input clock, reset;
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output [3:0] count;
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reg [3:0] count;
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always @(posedge clock) begin
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count <= count + 1;
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if (reset)
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count <= 0;
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end
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endmodule
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