yosys/tests/arch/intel_alm/quartus_ice.ys

read_verilog <<EOT
// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
module top();
  (* keep *) wire [31:0] \a[10] ;
  (* keep *) wire b;
  assign b = \a[10] [31];
endmodule
EOT

synth_intel_alm -family cyclonev -quartus
select -assert-none w:*[* w:*]*

design -reset
read_verilog <<EOT
// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
module top();
  (* keep *) wire [31:0] \a[10] ;
  (* keep *) wire b;
  assign b = \a[10] [31];
endmodule
EOT

synth_intel_alm -family cyclone10gx -quartus
select -assert-none w:*[* w:*]*