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synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev
async2sync
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-count 6 t:MISTRAL_FF
Replace opt_rmdff with opt_dff.
2020-07-20 16:19:51 -05:00
select -assert-max 1 t:MISTRAL_NOT
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
Replace opt_rmdff with opt_dff.
2020-07-20 16:19:51 -05:00
select -assert-max 1 t:MISTRAL_ALUT3
select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
synth_intel_alm: Use dfflegalize.
2020-06-30 20:31:34 -05:00
select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
tests: update fsm.ys resource count Suspect it is to do with map/set ordering in techmap; should be fixed by #1862?
2020-05-27 14:49:16 -05:00
select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
Replace opt_rmdff with opt_dff.
2020-07-20 16:19:51 -05:00
select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
intel_alm: add Cyclone 10 GX tests
2020-07-05 12:53:14 -05:00
design -reset
read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx
async2sync
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-count 6 t:MISTRAL_FF
Replace opt_rmdff with opt_dff.
2020-07-20 16:19:51 -05:00
select -assert-max 1 t:MISTRAL_NOT
intel_alm: add Cyclone 10 GX tests
2020-07-05 12:53:14 -05:00
select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
select -assert-max 2 t:MISTRAL_ALUT3 # Clang returns 2, GCC returns 1
Replace opt_rmdff with opt_dff.
2020-07-20 16:19:51 -05:00
select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
intel_alm: add Cyclone 10 GX tests
2020-07-05 12:53:14 -05:00
select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
Replace opt_rmdff with opt_dff.
2020-07-20 16:19:51 -05:00
select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D