yosys/tests/arch/common/tribuf.v

module tristate(en, i, o);
    input en;
    input i;
    output reg o;

    always @(en or i)
        o <= (en)? i : 1'bZ;
endmodule
Unify verilog style 2019-10-18 05:50:24 -05:00			`module tristate(en, i, o);`
Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. 2019-09-23 07:51:41 -05:00			`input en;`
			`input i;`
			`output reg o;`
Unify verilog style 2019-10-18 05:50:24 -05:00
Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. 2019-09-23 07:51:41 -05:00			`always @(en or i)`
Unify verilog style 2019-10-18 05:50:24 -05:00			`o <= (en)? i : 1'bZ;`
Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. 2019-09-23 07:51:41 -05:00			`endmodule`