mirror of https://github.com/YosysHQ/yosys.git
35 lines
935 B
VHDL
35 lines
935 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity top is
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port (
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clk : in std_logic;
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rst : in std_logic;
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up : in std_logic;
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down : in std_logic;
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cnt : buffer std_logic_vector(7 downto 0)
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);
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end entity;
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architecture rtl of top is
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begin
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process (clk) begin
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if rising_edge(clk) then
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if rst = '1' then
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cnt <= std_logic_vector(to_unsigned(0, 8));
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elsif up = '1' then
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cnt <= cnt + std_logic_vector(to_unsigned(1, 8));
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elsif down = '1' then
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cnt <= cnt - std_logic_vector(to_unsigned(1, 8));
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end if;
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end if;
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end process;
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-- PSL default clock is (rising_edge(clk));
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-- PSL assume always ( down -> not up );
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-- PSL assert always ( up |=> (cnt = prev(cnt) + std_logic_vector(to_unsigned(1, 8))) ) abort rst = '1';
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-- PSL assert always ( down |=> (cnt = prev(cnt) - std_logic_vector(to_unsigned(1, 8))) ) abort rst = '1';
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end architecture;
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