mirror of https://github.com/YosysHQ/yosys.git
12 lines
179 B
Coq
12 lines
179 B
Coq
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module NegEdgeClock(q, d, clk, reset);
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input d, clk, reset;
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output reg q;
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always @(negedge clk or negedge reset)
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if(!reset)
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q <= 1'b0;
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else
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q <= d;
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endmodule
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