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15 lines
191 B
Systemverilog
15 lines
191 B
Systemverilog
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module test (
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input ia,
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output oa,
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input [0:0] ib,
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output [0:0] ob,
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input [3:0] ic,
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output [3:0] oc
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);
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assign oa = ia;
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assign ob = ib;
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assign oc = ic;
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endmodule
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