mirror of https://github.com/YosysHQ/yosys.git
24 lines
728 B
Verilog
24 lines
728 B
Verilog
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module reset_test #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
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(input clk,
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input [CTRLW-1:0] ctrl,
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input [DINW-1:0] din,
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input [SELW-1:0] sel,
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output reg [WIDTH-1:0] dout);
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reg [SELW:0] i;
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wire [SELW-1:0] rval = {reset, {SELW-1{1'b0}}};
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localparam SLICE = WIDTH/(SELW**2);
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// Doing exotic reset. masking 2 LSB bits to 0, 6 MSB bits to 1 for
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// whatever reason.
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always @(posedge clk) begin
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if (reset) begin: reset_mask
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for (i = 0; i < {SELW{1'b1}}; i=i+1) begin
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dout[i*rval+:SLICE] <= 32'hDEAD;
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end
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end
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//else begin
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dout[ctrl*sel+:SLICE] <= din;
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//end
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end
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endmodule
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