mirror of https://github.com/YosysHQ/yosys.git
59 lines
1.6 KiB
C++
59 lines
1.6 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/rtlil.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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PRIVATE_NAMESPACE_BEGIN
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USING_YOSYS_NAMESPACE
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#include "ql_dsp_pm.h"
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struct QlDspPass : Pass {
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QlDspPass() : Pass("ql_dsp", "pack into QuickLogic DSPs") {}
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void execute(std::vector<std::string> args, RTLIL::Design *d) override
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{
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log_header(d, "Executing QL_DSP pass. (pack into QuickLogic DSPs)\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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break;
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}
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extra_args(args, argidx, d);
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for (auto module : d->selected_modules()) {
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{
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ql_dsp_pm pm(module, module->selected_cells());
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pm.run_ql_dsp_pack_regs();
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}
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{
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ql_dsp_pm pm(module, module->selected_cells());
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pm.run_ql_dsp_cascade();
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}
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{
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ql_dsp_pm pm(module, module->selected_cells());
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pm.run_ql_dsp_pack_regs();
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}
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}
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}
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} QlDspPass;
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PRIVATE_NAMESPACE_END
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